Top Perl Jobs in San Francisco Bay Area
Join a distributed team as a senior ASIC Physical Design Engineer to develop the next generation of mining ASIC. Responsibilities include block level physical implementation, timing closure, custom cell development, and enhancing design infrastructure. Requires expertise in Synopsys ICC2/Fusion Compiler and PrimeTime, experience with chip delivery, and strong scripting skills.
As a senior ASIC Physical Design Engineer, you will work on developing the next generation of mining ASICs, focusing on block level physical implementation, timing, integration, and verification. The role involves collaborating with digital and mixed signal designers and enhancing design flows and infrastructure.
Seeking DevOps Engineers passionate about marrying data with emerging technologies. Collaborate with Agile teams, design, develop, test, and support technical solutions in full-stack development tools. Share passion for tech trends, experiment with new technologies, and mentor engineering community. Deliver cloud-based solutions and drive transformative experiences.
Design and deploy networks based on business and technical requirements, troubleshoot and resolve network issues, participate in planned change introduction to production environment, provide mentorship, collaborate with teams for software code upgrades and device maintenance.
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CrowdStrike is looking for an Engineer II to join their Production Systems team. The role involves designing and implementing data pipelines, resolving discrepancies between data sources, and developing automated quality checks. The ideal candidate should have experience with automation scripting, RDBMS, network and systems infrastructure, and operating systems like VMware, Windows, and Linux.
Infrastructure Linux Engineer responsible for supporting corporate infrastructure by managing Linux Operating Systems, automation tasks, migration of servers, security hardening, VM management, and system performance monitoring.
Join Apple as an ASIC Integration Engineer responsible for full chip and block level timing closure ownership, generating timing constraints, and working on complex SoCs for high-end mobile applications. Bring your expertise in various methodologies and tools to help deliver the next phenomenal Apple product.
Seeking an outstanding engineer to support hardware and software vertical integration for the Dojo Fabric Team. Responsibilities include developing firmware drivers, customizing libraries, designing PCB network interface cards, and executing machine learning algorithms on the Dojo supercomputer.
As a Fastly Cloud Engineer, you will be responsible for building technical relationships with customers, implementing Fastly products, recommending improvements, and tracking customer accounts' health. This hands-on role requires expertise in networking and experience with various technologies.
Lead and perform safety analysis of FPGA subsystems and develop features with a focus on functional safety and reliability.
Lead the design, implementation, and maintenance of Ripple's global network infrastructure, ensuring security and scalability. Provide technical leadership, network monitoring, and mentorship to support operations.
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