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Tarana Wireless, Inc.

Senior ASIC Verification Engineer

Job Posted 3 Days Ago Reposted 3 Days Ago
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Milpitas, CA
130K-175K Annually
Senior level
Milpitas, CA
130K-175K Annually
Senior level
The Senior ASIC Verification Engineer will verify SoCs for broadband wireless access, collaborating with various engineering teams to develop verification strategies and methodology.
The summary above was generated by AI


Do you think coding solves 99% of tech issues then this is the place for you in a highly collaborative environment.  You will get to touch so many different UVM modules that you will make such an impact on our products.  We are looking for someone that is self driven however knows when to collaborate to solve problems.  
This position will verify the world’s most powerful SoCs for broadband wireless access that will connect the world wirelessly with fiber-class speed, on both Line of Sight and Non Line of Sight connections.

 

What you’ll be doing:

  • Work with some of the best DSP, system, and software engineers to define verification strategies and execute plans at system or full chip level
  • Build and continuously improve verification infrastructure and methodologies to meet the demands of next generation SoCs
  • Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project

 

Ways to stand out from the crowd:  

  • Ability to handle complex and hard-do-solve problems in programming and verification
  • Ambitious and dedicated
  • Good interpersonal skills
  • Solid knowledge and strong experience of System Verilog, UVM, and C/C++
  • Experience with building abstraction layered and reusable verification testbench infrastructure
  • Working knowledge of scripting languages such as Python


Required Skills & Experience:

  • BSEE required/MSEE preferred
  • 5-12 years of related Verification experience 
  • Strong knowledge of UVM
  • Proficiency with at least one of these: C++, Object Oriented Programming, System Verilog
  • Strong knowledge on basic concepts of VLSI, SoC architecture
  • Ethernet and packet processing experience
  • Exceptional analytical skills and problem-solving skills

 

The salary range for this position is: $130,000 to $175,000
Compensation will be determined based on several factors including, but not limited to: skill set, years of experience and the employee’s geographic location.
Tarana provides competitive benefits to employees in this role including: Medical, dental and vision benefits, 401K match, flexible time off and stock option.   
 

Top Skills

C++
Python
System Verilog
Uvm
HQ

Tarana Wireless, Inc. Milpitas, California, USA Office

590 Alder Dr, Milpitas, California, United States, 95035

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