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MatX

Silicon Design-for-Test (DFT) Engineer

Job Posted 16 Days Ago Reposted 16 Days Ago
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Mountain View, CA
Mid level
Mountain View, CA
Mid level
The role involves implementing DFT for silicon products, integrating DFT solutions, and collaborating with design teams to optimize performance and functionality.
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MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes.

In this role you will:

  • Execute MatX’s DFT implementation/verification and collaborate on physical design methodology from RTL to GDS.
  • Integrate DFT interfaces from IP blocks and develop pattern porting flow.
  • Identify and execute effective & efficient DFT solutions based on chip architecture.
  • Work closely with the design, verification and physical design co-owners of the subsystem/block and top-level on DFT verification and physical design considerations to deliver best-in-class performance-power-area results
  • Work with vendor and test partners to bring up test program on silicon towards production and NPI

Key Experience and requirements for this role:

  • DFT implementation (MBIST and At-speed Scan) and execution on large and complex ASICs and SOCs to production silicon
  • Experience with latest DFT technologies (like IJTAG, Streaming Scan, efficient memory repair)
  • DFT Flow automation and hands on experience with Tessent DFT & Fusion Compiler
  • Experience of working with a third-party design services partners to deliver tapeout-ready designs with DFT
  • Experience/familiarity of integration of PHY DFT interfaces
  • Knowledge of post-silicon DFT pattern bring-up

Compensation

  • The US base salary for this full-time position is $120,000 - $400,000 + equity

Benefits

  • Commuter stipend available for employees within 60 minutes of the office
  • 401(k) with contribution matching
  • Health, vision, and dental insurance
  • Life and AD&D insurance

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.


MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

Top Skills

Asic
At-Speed Scan
Dft
Fusion Compiler
Ijtag
Mbist
Soc
Streaming Scan
Tessent Dft
HQ

MatX Mountain View, California, USA Office

Mountain View, CA, United States

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