Sr. Timing lead

Job Details:

Job Description: 

Server group is looking for Sr Static Timing Analysis (STA) Lead to come and work on the latest server products. This requires technical leaders that can take product performance requirements and translate them into constraints, design and a high-quality deliverable.  You will be actively engaged in the overall SD execution and will be working tightly with Architecture, clocking, Logic and Physical Design teams.

We are looking for an SoC (System on Chip) Timing engineers with hands on experience and timing convergence success  on multiple SOC through TI.  

You will be responsible for, but not limited to:  

• Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.
• Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
• Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
• Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning.
• Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study, plus 10+ years of hands-on STA experience and proven SOC timing convergence record.
• OR Master's degree in Electrical / Computer Engineering, Computer Science, plus 8+ years of hands-on STA experience and proven SOC timing convergence record.

Preferred Qualifications:

• Leadership experience with performance verification (PV) methodology
• Experience in leading timing teams.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Massachusetts, Beaver Brook

Additional Locations:US, California, Santa Clara, US, Texas, Austin

Business group:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.