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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The intern will do research of advanced gate modeling for timing analysis and library characterization.
Position Requirements:
Solid knowledge of digital circuits, skillset to run circuit simulations, collecting and processing results using scripting (must).
Strong programming skills, fluency in Python (must)
Advanced level of statistics and probability theory (plus)
Minimum duration of internship is 2.5 months due to expected long ramp-up time
A full-time student pursuing a MS/PhD in computer science, statistics, computer engineering, or electrical engineering
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Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
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