Digital, Mixed Signal IC Design Engineer, Principal

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team making a big impact on this organization.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

ASIC design engineer responsible the development of behavior and timing models of high-performance SerDes analog circuits for use in digital and system verification.

The responsibilities include but not limited to.

• Develop accurate and simulation-efficient analog behavior models for SerDes analog circuits in SystemVerilog.
• Build accurate representations of analog schematic circuits and verify analog behavior model quality.
• Document modeling and verification results for formal review.
• Improve analog modelling design methodology and flow.
• Be a key contributor to bridge the gap between digital and analog design flow.
• Collaborate with Analog/Digital design teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre and post silicon

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
• Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience.
• Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC.
• Hands on experience in interpretive language such as Perl/Python.
• Proven track record of delivering production-quality designs on aggressive development schedules.
• Domain expertise in IEEE/UCIe/CXL/PCIe protocols, DDR memory controllers is a plus.

Expected Base Pay Range (USD)

146,850 - 220,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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